Major combined electrolyte deficiency during therapy with low-dose Cisplatin, 5-Fluorouracil and Interferon alpha: report on several cases and review of the literature [ISRCTN62866759]

BACKGROUND: Low-dose Cisplatin and Interferon alpha treatment of solid tumors rarely has been associated with severe hypocalcaemia. To the authors knowledge the phenomenon has not been reported previously in patients with pancreatic carcinoma. CASE PRESENTATION: A patient with resected adenocarcinoma of the pancreas was treated with adjuvant radio-chemo-immunotherapy using a combination of low-dose Cisplatin, 5-Fluorouracil and Interferon alpha together with external beam radiation. Severe hypocalcaemia without signs of acute renal failure or electrolyte disturbance occurred within 2 days at the 4th week of treatment and required intensive care treatment. CONCLUSION: Combination of biological and cytotoxic therapies may increase the incidence of severe hypocalcaemia in pancreatic cancer. Oncologists should remain attentive of this problem as more highly active regimes become available

Spatial: A Language and Compiler for Application Accelerators

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for productivity and are difficult to target from higher level languages. HLS tools are more productive, but offer an ad-hoc mix of software and hardware abstractions which make performance optimizations difficult.In this work, we describe a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators. We describe Spatial's hardware-centric abstractions for both programmer productivity and design performance, and summarize the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning. We demonstrate the language's ability to target FPGAs and CGRAs from common source code. We show that applications written in Spatial are, on average, 42% shorter and achieve a mean speedup of 2.9x over SDAccel HLS when targeting a Xilinx UltraScale+ VU9P FPGA on an Amazon EC2 F1 instance